Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a damascene bit line.
As the integration degree of memory devices is increasing, formation of a self-aligned contact process for a storage node contact plug after forming a bit line contact plug and a bit line is becoming more difficult. In sub-30 nm memory devices, open space of a storage node contact hole has been difficult to secure and a self-aligned contact fail (SAC fail) occurs frequently due to decreases in process margins.
In order to address such features, a damascene bit line process is used in which a storage node contact plug is first formed and a bit line is subsequently formed.
The damascene bit line process is performed as follows.
First, a dual storage node contact hole is formed in which two adjacent storage node contact plugs are formed simultaneously. More specifically, a storage node contact plug is first formed to be buried in the dual storage node contact hole. Through a damascene process, the storage node contact plug is separated. A bit line is formed to fill a damascene pattern.
In the damascene bit line process, patterning may be easily performed in comparison with when storage node contact plugs are individually formed. Furthermore, self-aligned contact fail occur less frequently compared with a process in which storage node contact plugs are formed later. Furthermore, when the storage node contact plugs are first formed and bit lines are later formed, a short circuit between the storage node contact plug and a word line and a short circuit between the storage node contact plug and the bit line may be prevented.
FIG. 1 is a photograph illustrating a conventional method for forming a damascene bit line.
Referring to FIG. 1, when a damascene pattern is formed, a dual storage node contact plug is etched (see 12), and an interlayer dielectric layer is simultaneously etched (see 11). For example, the interlayer dielectric layer is first etched to open a first damascene pattern 11, and the dual storage node contact plug is subsequently etched to open a second damascene pattern 12. Therefore, the first and second damascene patterns 11 and 12 are coupled to form a line shape, and a bit line is subsequently formed in the damascene patterns.
In the conventional method, however, when the dual storage node contact plug is etched, the first damascene pattern 11 is additionally etched. Here, the bottom of the first damascene pattern 11 is damaged (see B). Accordingly, the etching process of the first damascene pattern 11 may not be sufficiently performed. Since the etching process is not sufficiently performed, the bottom profile of the first damascene pattern 11 may be sloped, and a bottom open critical dimension (CD) may not be secured.
In order to prevent the first damascene pattern 11 from causing damages, the etching amount of the second damascene pattern 12 may be reduced and thus, the storage node contact plug may not be easily separated (see A).